Here's a classic run down of the two stage opamp. As a circuit designer, these fundamentals should be engrained. At a reputable company, probably at least 75% of these would be asked.

1. Draw the basic CMOS two stage opamp.
2. Label the inputs and outputs. Which input is the positive input?
3. How do you know this is the correct positive input?
4. Why would you use two stages instead of only one?
5. What input differential pair FET type would you use? PFET or NFET? Why?
6. In DC normal operation, What is the input resistance?
7. In DC normal operation, What is the output resistance?
8. What are the input and output voltage operating ranges/swings?
9. If the input voltages are equal, and set such that all the transistors are in saturation. What is the voltage at the gate of the second stage input?
10. What is the DC open loop gain?
11. How would you increase the gain?
12. Does increasing the 1st stage current increase or decrease the gain? Why is that?
13. What is the dominant pole of a Miller compensated two stage opamp?
14. What is the Miller compensation?
15. What is the second dominant pole?
16. What is the third dominant pole?
17. Why do people usually not worry about the third pole?
18. Is it possible to do o
19. How much attenuation and phase shift does one pole give?
20. For one pole, can the phase shift reach 90 degrees?
21. What is the gain bandwidth product of the two stage opamp?
22. Where is the second stage zero?
23. Is this zero good or bad? Why?
24. Do you know techniques to deal with this zero?
25. If a nulling resistor is used, do you use a resistor or transistor?
26. Would you put this resistor or transistor on the left or right side of the compensation capacitor? Why?
27. What can you do to make your two stage opamp more stable?
28. What is the positive slew rate?
29. What is the negative slew rate?
30. How can you increase slew rate?
31. What is the common mode rejection ratio (CMRR)?
32. Does CMRR get better or worse as you increase frequency? Why?
33. What is power supply rejection ratio (PSRR)?
34. Write the positive and negative PSRR equations.
35. How does the Miller capacitance affect PSRR?
36. What's the input offset mismatch?
37. How do you ratio the stage 1 and stage 2 currents to reduce systematic offset?
38. How would you decrease random mismatch? What drawbacks are there?
39. How does each transistor in the first stage contribute to the input-referred noise?
40. How would you decrease the input-referred noise? What are the drawbacks?
41. Explain the difference between flicker and thermal noise.
42. Floorplan a two stage opamp layout.
43. Which devices should be matched?